1. Field of the Invention
The present invention relates to integrated circuit package design and, more particularly, to synthesizing information about signal nets from multiple integrated circuit package models.
2. Related Art
Integrated circuits (ICs) are becoming increasingly large and complex, typically including millions of individual circuit elements such as transistors and logic gates. As a result of this increased size and complexity, IC designers are increasingly using electronic design automation (EDA) software tools to assist with IC design. Such tools help to manage the complexity of the design task in a variety of ways, such as by allowing ICs to be designed hierarchically, thereby enabling the design to be divided into modules and enabling the design task to be divided among multiple designers in a manner that limits the complexity faced by any one designer.
Various hardware description languages (HDLs) have been developed which allow circuit designs to be described at various levels of abstraction. A description of a circuit according to an HDL (referred to herein as an xe2x80x9cHDL modelxe2x80x9d of the circuit) may, for example, describe a particular circuit design in terms of the layout of its transistors and interconnects on an IC, or in terms of the logic gates in a digital system. Descriptions of a circuit at different levels of abstraction may be used for different purposes at various stages in the design process. HDL models may be used for testing circuits and circuit designs, as well as for fabricating the circuits themselves. The two most widely-used HDLs are Verilog and VHDL (Very High Speed Integrated Circuits (VHSIC) Hardware Description Language), both of which have been adopted as standards by the Institute of Electrical and Electronics Engineers (IEEE). VHDL became IEEE Standard 1076 in 1987 and Verilog became IEEE Standard 1364 in 1995.
EDA tools are typically capable of converting a functional HDL description of a circuit design into a specific circuit implementation. The specific circuit implementation may be represented by a xe2x80x9cnetlist,xe2x80x9d which identifies both the elements of the circuit and the interconnections among them. In general, a netlist describes the circuit design in terms of nodes and edges. Each node represents a circuit element and each edge represents an interconnection between two circuit elements. Netlists may describe circuits at various levels of abstraction. A netlist may, for example, describe circuit elements in terms of specific structural components (such as resistors and transistors) or in terms of high-level xe2x80x9ccellsxe2x80x9d that may be decomposed into specific structural components and/or other cells. A netlist may, for example, describe the connections between cells in terms of specific cell-to-cell pin connections.
EDA tools are typically capable of converting a netlist into a physical layout of the circuit. The layout process involves both xe2x80x9cplacementxe2x80x9d (assigning specific coordinates in the circuit layout to each cell) and xe2x80x9croutingxe2x80x9d (wiring or connecting cells together). The layout produced thereby defines the specific dimensions and coordinates of the gates, interconnects, contacts, and other elements of the circuit. The layout may have multiple layers, corresponding to the layers of the circuit. The layout may be used to form a mask, which in turn may be provided to a foundry to fabricate the integrated circuit itself.
One stage in the process of IC design is package design, which refers to the design of substrates (packages) for interconnecting layers of the IC. An IC typically includes multiple packages interconnected in layers. Each package, in turn, may include multiple layers. Packages within a single IC may be composed of varying materials having varying electrical properties. Individual signal nets (also referred to herein simply as xe2x80x9cnetsxe2x80x9d) in the IC may be distributed across multiple packages. A package design must ensure that signals in the IC have sufficient power and maintain sufficient signal integrity when passing from one layer of the IC to another. As used herein, the term xe2x80x9csignal netxe2x80x9d (or simply xe2x80x9cnetxe2x80x9d) refers to a collection of conductors that are connected to form a complete circuit connecting at least one output to at least one input.
As with IC design more generally, various tools exist for automating aspects of IC package design. Such tools typically provide a graphical user interface through which package designers may visually design the IC package in three dimensions. One such tool is Advanced Package Designer (APD), available from Cadence Design Systems, Inc. of San Jose, Calif. APD is a software program which allows the package designer to model the physical, electrical, and thermal characteristics of the package substrate. An APD package design database may be provided to a foundry to be used directly as manufacturing input for fabrication of the designed package.
Referring to FIG. 1, relevant features of a conventional system 100 for designing IC packages are illustrated in block diagram form. A package design tool (not shown), such as APD, maintains a plurality of package models 102a-n, each of which contains information defining a particular package in an IC design. The package models 102a-n may include, for example, information specifying the name, location, and length of each signal trace in each layer of the package models 102a-n. Each of the package models 102a-n is typically stored in a distinct database file in a computer system.
Package design tools typically allow a package designer to access and modify only a single one of the package models 102a-n at a time. To modify a particular one of the package models 102a-n, the package designer must typically use the package design tool to open the database file corresponding to the package model to be modified. Upon opening one of the package models 102a-n, the package design tool may provide a graphical user interface which displays a two-dimensional or three-dimensional representation of the package model and which allows the package designer to modify the package model. Techniques for creating and modifying packages using such package design tools are well-known to those of ordinary skill in the art. To modify a different one of the package models 102a-n, the package designer must typically close the current package model and use the package design tool to open the other package model.
Package design tools are typically capable of generating various kinds of reports containing information about the package models 102a-n. One such report is a net length report, which contains information about the package-specific (intra-package) path length of each signal net within a particular one of the package models 102a-n. In other words, for each signal net within a particular package, the net length report indicates the length of that portion of the signal net which runs through the package. Such a report is therefore referred to herein as a xe2x80x9cpackage-specific net length report.xe2x80x9d
For example, as shown in FIG. 1, a net length report generator 104 (which may, for example, be part of the package design tool that was used to design the package models 102a-n) generates package-specific net length reports 108a-n, each of which contains the package-specific path lengths of signal nets within a corresponding one of the package models 102a-n. For example, package-specific net length report 108a contains the package-specific path lengths of signal nets within package model 102a. 
The package-specific net length reports 108a-n may include various kinds of information about the path lengths of signal nets in the package models 102a-n. In their simplest form, for example, each of the package-specific net length reports 108a-n may contain a list of the names of all of the signal nets in the corresponding package model and the path length of each such signal net within the corresponding package model. A more detailed report may include information not only about the path length of each signal net within a package, but also information about the length of each signal net within each layer of the package.
It is often desirable or necessary to synthesize information about multiple ones of the package models 102a-n. For example, it may be desirable or necessary to calculate the total path lengths of signal nets through all of the package models 102a-n, or to calculate the total propagation delays of signal nets through all of the package models 102a-n. Such information synthesis is useful, for example, to perform length equalization (also referred to as xe2x80x9cskew equalizationxe2x80x9d), which involves equalizing the path lengths of multiple signal nets in a group of signal nets. It may also be desirable to ensure that signal nets within particular signal net groups have the same total propagation delay through the IC within a specified tolerance. Conventional package design tools typically are not capable of performing such information synthesis automatically because they operate on only one of the package models 102a-n at a time. As a result, it typically is necessary for package designers to calculate total signal net path lengths and propagation delays manually, which is a tedious, time-consuming, and error-prone process.
What is needed, therefore, are improved techniques for synthesizing information about signal nets from multiple package models.
Techniques are disclosed for automatically synthesizing information from a plurality of computer-readable integrated circuit package models. In one embodiment, each of the plurality of package models contains information descriptive of a distinct package. Such information may include, for example, intra-package path lengths and/or propagation delays of signal nets in the modeled packages. Techniques are disclosed for automatically synthesizing such information to produce, for example, aggregate path lengths and/or propagation delays of the signal nets across all of the modeled packages. Such synthesis may be performed even when the package models use mutually inconsistent signal net naming conventions and the modeled packages are composed of different materials. Techniques are also disclosed for providing information to the package designer to assist the package designer in improving the design of the package models.
In one aspect of the present invention, a method is provided for use in a system is provided which includes a plurality of models of integrated circuit packages. The plurality of models include package-specific values of a property (such as signal net path length and/or signal net propagation delay) of a plurality of signal nets in the integrated circuit packages. The method includes steps of: (A) selecting a first one of the plurality of signal nets; (B) selecting, from a first one of the plurality of models, a first package-specific value of the property of the first signal net; (C) selecting, from a second one of the plurality of models, a second package-specific value of the property of the first signal net; and (D) applying a synthesis function (such as addition) to the first and second package-specific values to produce a synthesized property value.
In another aspect of the present invention, a method is provided for use in a system including a plurality of property values of a plurality of signal nets in an integrated circuit. The method includes steps of: (A) identifying a reference value r; and (B) for each property value S in the plurality of property values (e.g., signal net path lengths and/or signal net propagation delays), performing steps of: (1) determining whether property value S differs from reference value r by more than a predetermined amount; and (2) notifying a user of the system if it is determined that the property value S differs from the reference value r by more than the predetermined amount. The reference value r may be selected from among the plurality of property values.
In yet another aspect of the present invention, a method is provided for use in a system including a plurality of property values of a plurality of signal nets in an integrated circuit. The method comprises steps of: (A) identifying a reference value r; and (B) for each property value S in the plurality of property values, performing steps of: (1) identifying a difference D between property value S and reference value r; and (2) notifying a user of the system of the difference D.
Other features and advantages of various aspects and embodiments of the present invention will become apparent from the following description and from the claims.